PN3033M, a superior system on chip for DRM30 / DRM+ application
There is no attach data.
Environmental Matter : RoHs CompliancePb Free Compliance

Chip Overview :
 PN3033M is a superior system on chip for DRM30/DRM+ applications.
It fully supports the Digital Radio Mondiale [DRM] consists of flexible hardware COFDM demodulator and RADIO DSP.
Several interfaces such as SPI, I2C and are implemented providing customers with more flexibility.
 The PN3033M integrates the Tensilica 330HiFi DSP, offering the low-power, high-performance audio DSP cores, support enhanced digital audio applications. The 330HiFi DSP core eliminates the need for the audio companion processors normally required for audio-based applications.
By removing the need for costly application coprocessors and memory subsystems, the PN3033M chipset solution reduces BOM costs.
The PN3033M chipset solution integrates both DRM30 and DRM+ into a single chip.


 Multi-standards support: DRM30/DRM+
 Differential 12-bits ADC for demodulator and Digital Tuner interfac
 Outstanding SFN, Mobility, Adjacent and Co-channel rejection
 Ideal C/N Performance and Superior Fading Performance
 Auto detect of transmission mode and guar
 Decoding Information: FAC, SDC and MS
 Low power consumption: 150mW(TBD)
 32-bits RISC architecture with integrated 24-bits audio processing instructions
 Modeless switching between 16-, 24-, and 64-bits dual-issue instructions
 Dual MACs can operate as 32 x 16-bits/24 x 24-bits
 4KByte Instruction and 8KByte data 2-way set associative caches
 48KByte data RAM and 128KByte SRAM for system process
 PN3033M: 2MByte Mobile SDRAM stacked (TBD) for high technology audio codec process and data service
 10 x 10 mm, 0.8 mm pitch, 128-pins Fine Pitch BGA technology.

 All in one for DAB/DAB+/DMB-Audio receivers.
 Flexible Data Service (TPEG,EPG,etc) process with SPI master mode interface.
 Application software is available with full supports.
 16MByte SDRAM stacked for DAB+/DMB-Audio application.
 PnpNetwork provides a full SDK solution for easy development environment and flexibility to design.
 AEC-Q100 Certification on progress.

Ordering Information
Order Number


Stacked SDRAM Size


Package Information

Ball Pitch


Body Size

10mm x10mmx1.3mm

Pin Count (Type)

128 pins (FBGA)

Supply Voltage




2.7 ~ 3.6V

Core Clock Speed

300MHz (TBD)

Operation Temperature

-40 ~ +85oC (TBD)

Storage Temperature

-40 ~ +125oC

※ Note: PN3033M is pin-to-pin compatible with PAIOSx-V / PAIOSx-A series.